is the dragonfly’s visual interception reflex — a neural circuit that has computed predictive motion since the Carboniferous period. Its medium is synthesizable Verilog RTL. Its output, produced in 25 nanoseconds, is a coordinate: where a moving object will be.
The architecture does not interpret. It does not learn. It measures, delays, correlates, and predicts through a fixed seven-stage pipeline. This determinism is the work’s central property.
The biological model — the Hassenstein-Reichardt correlator, the T4/T5 dendritic mechanism, the confidence-gated burst encoding — is not metaphor. It is the specification. The distance between the dragonfly’s optic lobe and this RTL is a translation, not an interpretation.
The work exists in three simultaneous registers. As engineering: a functional, FPGA-implemented hardware core.
The dragonfly’s aerial hunting strategy is predictive. It computes an intercept. Flight paths recorded in laboratory conditions are consistent with a constant-bearing, decreasing-range pursuit geometry — the geometry of prediction rather than reaction. The neural substrate responsible, target-selective descending neurons (TSDNs), projects from the optic lobe directly to flight motor circuits. Observation, computation, and action are one continuous process.
Hassenstein and Reichardt derived a model of directional motion detection from purely behavioural experiments on walking beetles. No electrophysiology. A logical argument from stimulus to response. The model specifies: delay the signal from one photoreceptor, multiply it with the instantaneous output of an adjacent one, subtract the mirror-symmetric subunit. The result is direction-selective. Confirmed without modification in electrophysiology decades later. It remains the governing framework.
T4 neurons (ON edges) and T5 neurons (OFF edges) in the Drosophila optic lobe each come in four subtypes tuned to one of four cardinal directions. Directional sharpness arises from a dual mechanism on the same dendritic tree: preferred-direction enhancement via GluCl-α receptors at the dendritic tips, null-direction suppression via GABA-A receptors at the base. Mi9, Mi1, and Mi4 provide excitatory and inhibitory inputs at precisely mapped spatial locations. The geometry of the dendrite performs the computation. No learning. No weights. Fixed physics.
Out-of-context implementation was completed on Xilinx UltraScale+ VU9P at 200 MHz for both the bare core and an AXI-integrated evaluation shell. Both builds achieved positive setup and hold slack with zero routing errors. These are out-of-context results: materially stronger than simulation-only evidence, but not equivalent to full board-level timing closure. That distinction is stated explicitly here and in the package documentation.
| Claim | Specification | Result | Testbench |
|---|---|---|---|
| Latency | ≤ 6 cycles @ 200 MHz | 5 cycles · 25 ns | tb_latency |
| Accuracy | ±2 px @ 300 Hz | 0 violations | tb_px_bound_300hz |
| Throughput | 1 Meps, zero drops | 2000 / 2000 ACK | tb_aer_throughput_1meps |
| Power scaling | Activity-proportional | Low/high confirmed | tb_power_lo · tb_power_hi |
| 8-direction motion | Cardinal + diagonal | All 8 axes exercised | tb_reichardt_ds |
| Outlier rejection | Coast on bad measurement | Confirmed | tb_ab_predictor |
| Hysteresis gating | Stable gate behaviour | Confirmed | tb_burst_gate |
| Full suite | 26 testbenches | 26 / 26 | make run-once |
AER → LIF tile → 8-direction delay lattice → Reichardt direction selector → burst gate → α–β predictor → confidence gate. Fixed feed-forward architecture. Click any stage to expand.
4-phase handshake receiver (REQ↑, ACK↑, REQ↓, ACK↓). Interoperates with Prophesee EVK4/IMX636, iniVation DAVIS346, Samsung DVS. No events dropped under sustained load.
Time-multiplexed, 14-bit. Filters incoherent events. Analogue to temporal filtering in medulla intrinsic neurons Mi1, Mi4, Mi9.
Ring-buffer delay lattice across cardinal (E, W, N, S) and diagonal (NE, NW, SE, SW) axes. Diagonal contributions scaled for geometric equivalence approximation.
Implements both preferred-direction enhancement and null-direction suppression — direct analogue of T4/T5 dendritic computation. All eight axes exercised in tb_reichardt_ds.
Hysteretic density thresholding. TH_OPEN=3, TH_CLOSE=1. Only sustained coherent activity propagates to the predictor.
Q8.8 fixed-point. Forward extrapolation: p̂ = p + v·Δt. Outlier rejection above OUTLIER_TH=128; predictor coasts on current velocity estimate.
Reliability score from event rate and direction magnitude across all eight axes. Gates output with pred_valid strobe. Downstream: (x̂, ŷ, conf).
Standard 4-phase AER handshake. Validated at ≥106 events/s with zero drops. Behavioural shell for FPGA bring-up; ASIC integration follows same semantics.
Single accumulator shared across spatial array via time-multiplexing. 14-bit precision. Configurable leak rate. Filters sparse or incoherent events.
Ring-buffer delay lattice, cardinal and diagonal axes. Diagonal contributions scaled for geometric equivalence. Provides temporal gradient structure for reichardt_ds.
Preferred-direction enhancement and null-direction suppression. Direct computational analogue of T4/T5 dendritic physics. All eight axes in tb_reichardt_ds.
TH_OPEN=3, TH_CLOSE=1. Reduces chatter at threshold boundary. Only sustained activity propagates to the predictor.
Trajectory extrapolation in continuous time. Outlier rejection: residuals above OUTLIER_TH=128 cause the predictor to coast on current velocity. ≤ ±2 px @ 300 Hz verified.
Reliability score across all eight axes. Downstream receives (x̂, ŷ, conf) only on pred_valid strobe.
| Parameter | Default | Description |
|---|---|---|
| XW / YW | 10 | Coordinate width, bits |
| AW | 8 | LIF address width |
| DW | 6 | Delay lattice depth, bits |
| PW | 16 | Predictor output width, bits |
| WINDOW | 16 | Burst gate counting window |
| TH_OPEN | 3 | Events to open burst gate |
| TH_CLOSE | 1 | Events to hold gate open |
| OUTLIER_TH | 128 | Residual threshold; predictor coasts above this |
LIBELLULA requires DVS cameras. It operates on asynchronous spike events — one per pixel per polarity change, timestamped to the microsecond. Frame-based cameras cannot provide the temporal precision required by the delay lattice and Reichardt correlator. This is a property of the architecture, not a limitation of the implementation.
Neural networks operating on event-camera streams batch or accumulate events before inference. Even purpose-built SNN inference takes on the order of 100 µs to several milliseconds to produce a position estimate. LIBELLULA produces a forward-extrapolated coordinate in 25 ns. These are complementary operations. LIBELLULA can supply a stable, direction-confirmed signal to an AI layer rather than raw accumulated events.
System-level latency figures used for comparison rows. LIBELLULA figures from simulation and out-of-context implementation. The forward prediction horizon is selectable via Δt and remains a roadmap item beyond the current validated core.
| System | Core latency | Forward forecast | Power |
|---|---|---|---|
| DJI / Skydio commercialFrame CNN on ARM + GPU | 20–40 ms | Reactive only | 3–8 W |
| ETH-UZH event-camera avoidanceScience Robotics, 2020 | 3.5 ms | None | ~10 W |
| FPGA event-vision acceleratorBonazzi et al., arXiv 2024 | ~2 ms | None | 3–5 W |
| LIBELLULA — core logicSynthesizable RTL · 200 MHz · UltraScale+ VU9P (OOC) | 25 ns (5 cycles) | 2–30 ms (Δt selectable) | 45–60 mW |
A self-contained engineering bundle. Addresses whether the RTL simulates coherently, synthesizes in a mainstream FPGA flow, places and routes cleanly, and provides an evaluator-friendly interface.
RTL source, testbenches, simulation Makefile, and implementation reports are available on GitHub. Technical engagement and access to the full evaluator package can be arranged directly.
Oliver Hockenhull · East Sooke, BC, Canada
oliver.hockenhull@gmail.com